A weight reload-free Compute-in-Read-Only-Memory (CiROM) architecture for billion-parameter LLM inference using 1.58-bit (ternary) weights. Integrates bidirectional ROM arrays, tri-mode local accumulators, and eDRAM KV-cache management, reducing external DRAM access by 43.6% during decoding. Achieves 20.8 TOPS/W and 10× area efficiency improvement over prior digital CiROM designs.